(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and, more particularly, to a method for making vertical and negative profiles in a patterned layer of photoresist.
(2) Description of the Prior Art
Photolithography is a common and well known approach whereby patterned layers of semiconductor material are typically formed by spinning a layer of photoresist over the surface of the semiconductor material, projecting light through a photomask having the desired pattern onto the layer of photoresist to expose the photoresist to the pattern, developing the photoresist, washing off the undeveloped photoresist and plasma etching to clean out the areas where the photoresist has been washed away. The exposed resist may be rendered soluble (positive working) and form the pattern, or insoluble (negative working) and be washed away. In either case, the remaining resist on the surface of the semiconductor material forms the desired pattern. The application of photoresist brings with it exposure of the processing environment to contamination from photoresist particulates and etchant solutions. To avoid this, dry etches may be employed but dry etches are expensive due to the high capitol cost Reactive Ion Etch (RIE) system and are limited in application because they require a hard mask such as nickel, aluminum or gold. Regardless of the material that is used for underlying conductive interconnects or the patterning techniques that are applied, planarization of the interlayer dielectric is crucial for obtaining a multilevel structure that allows accurate lithographic patterning. The deposition and etchback tolerances associated with large film thickness are cumulative, and any non-planarity of the photoresist is replicated in the final top surface of the device. Chemical-mechanical polishing is a fast and efficient approach for achieving planarity in multichip modules and integrated circuits.
One of the aspects that is associated with the use of photoresist is the stability of the applied layer of resist. Stability of a photoresist layer relates to its resistance to degradation of exposure and processing characteristics when the film is exposed to oxidants such as ambient oxygen after the film is removed from the deposition chamber. Typically, in commercial processes the film may not be developed immediately after exposure. Thus, if the film is not stable, the exposed pattern will degrade before the film is developed. High photosensitivity is required in commercial processes so that a short exposure time can be utilized for each substrate. In addition, high deposition rate of the deposited layer of photoresist is required for high throughput.
Wet etching is a frequently used technique for stripping photoresist films from silicon wafers where a complete removal of the resist images without adversely affecting the wafer surface is desired. The resist layer or images should he completely removed without leaving any residues, including contaminant particles that may have been present in the resist. The underlying surface of the photoresist layer should not be adversely affected, for instance, undesirable etching of the metal or oxide surface should he avoided. It is also desirable that the etching or stripping time should be reasonably short to permit a high wafer throughput.
It is for purposes of performance improvement frequently required to expose a surface over which a layer of photoresist has been deposited to elevated temperatures in order to improve processing conditions for the semiconductor device. Where this temperature exposure exceeds a limit of temperature, the layer of photoresist has a tendency to reflow. The invention uses photoresist reflow and provides a method where the wafer can be exposed to elevated temperatures for purposes of changing the profile of the openings created in the developed layer of photoresist. A conventional negative profile, with outwards sloping sidewalls, can be changed to a positive profile, with inwards sloping sidewalls or a profile having vertical sidewalls.
U.S. Pat. No. 5,849,435 (Akram et al.) shows a process, which inverts a wafer with resist and then hardens.
U.S. Pat. No. 6,100,506 (Colelli, Tr. et al.) shows a photoresist bake using a right side up hot plate.
U.S. Pat. No. 5,578,127 (Kimura) shows a coat and bake photoresist system.
U.S. Pat. No. 4,800,251 (Matsuoka) and U.S. Pat. No. 5,877,076 (Dai) are related processes with bakes and hot plates.